1. Field of the Invention
This invention relates to a nonvolatile semiconductor memory device capable of storing, for example, 2 bits or more of data.
2. Description of the Related Art
A nonvolatile semiconductor memory device capable of storing multivalued data, such as a NAND flash memory using EEPROM, has been proposed (U.S. Pat. No. 6,178,115).
In a NAND flash memory where a plurality of cells are arranged in a matrix, all of or half of the cells arranged in the direction of row are selected simultaneously. Data is written into or read from the selected cells in unison. Specifically, the selected cells are connected to corresponding bit lines. A latch circuit for holding the write and read data is connected to each bit line. Data is written or read by using the latch circuit.
This type of nonvolatile semiconductor memory device has been miniaturized so significantly that the spacing between adjacent cells in the row direction and the column direction is very narrow. As the distance between adjacent cells becomes shorter, the capacitance between the floating gates of adjacent cells (FG-FG capacitance) becomes larger. This causes the following problem: the threshold voltage Vth of a cell written into previously varies according to the data in an adjacent cell written into later due to the FG-FG capacitance. In the case of a multivalued memory that stores a plurality of data (k bits) in a single cell, it has a plurality of threshold voltages. Therefore, it is necessary to control the distribution of a threshold voltage per data very narrowly, which causes the following significant problem: the threshold voltage varies according to the data in the adjacent cells. Therefore, a nonvolatile semiconductor memory device capable of preventing the threshold voltage from varying with the data in the adjacent cells has been demanded.